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high accuracy, ultralow i q , 500 ma, anycap low dropout regulator data sheet adp3335 rev. d document feedback information furnished by analog devi ces is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without n otice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u. s.a. tel: 781.329.4700 ? 2000C 2013 analog devices, inc. all rights reserved. technical support www.analo g.com features high accuracy over line and load: 0.9% at 25c, 1.8% over temperature ultralow dropout voltage: 200 mv (typ ical ) at 500 ma requires only c o = 1.0 f for stability anycap ? = stable with any type of capacitor ( i ncluding mlcc) current and thermal l imiting low noise low shutdown current: < 10 na (typ ical ) 2.6 v to 12 v supply range C 40c to +85c ambient temperature range applications pcmcia cards cellular phones camcorders, cameras networking systems, dsl/cable modems cable set - top box mp3/cd playe rs dsp supplies functional block dia gram gm cc q1 in out nr r1 bandgap ref gnd sd adp3335 + ? r1 r2 00147-0-001 thermal protection driver figure 1 . nr in in out out out gnd sd adp3335 on off v in c in 1 f + + v out 00147-0-002 5 3 2 1 4 6 7 8 c out 1 f figure 2 . typical application circuit general description the adp3335 is a member o f the adp333x family of precision, low dropout, anycap voltage regulators. it operates with an input voltage range of 2.6 v to 12 v, and delivers a continuous load current up to 500 ma. the adp3335 stands out from conventional low dropout regulators (ldos) by using an enhanced process enabling it to offer performance advantages beyond its competition . its patented design requires only a 1.0 f output capacitor for stability. this device is insensitive to output capacitor equivalent series resistance (esr), and is stable with any good quality capacitor including ceramic (mlcc) types for space - restricted applications. the adp3335 achieves exceptional accuracy of 0.9% at room temperature and 1.8% over temperature, line, and load. the dropout voltage of the adp3335 is o nly 200 mv (typical) at 500 ma. this device also includes a safety current limit, thermal overload protection, and a shutdown feature. in shutdown mode , the ground current is reduced to less than 1 a. the adp3335 has a low quiescent current of 80 a (typical) in light load situations.
adp3335 data sheet rev. d | page 2 of 16 table of contents features .............................................................................................. 1 appl ications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revi sion history ............................................................................... 2 specifications ..................................................................................... 3 absolute maximum ratings ............................................................ 4 esd c aution .................................................................................. 4 pin configuration and function descriptions ............................. 5 typical performance characteristics ............................................. 6 theory of operation ........................................................................ 9 applications information .............................................................. 10 output capacitor selection ....................................................... 10 input bypass capacitor .............................................................. 10 noise reduction ......................................................................... 10 thermal overload protection .................................................. 10 calculating junction temperature ........................................... 10 printed circuit board layout considerations ....................... 11 lfcsp layout considerations .................................................. 11 shutdown mode ......................................................................... 11 outline dimensions ....................................................................... 12 ordering guide .......................................................................... 13 revision history 10/13 rev. c to rev. d updated outline dimensions ....................................................... 12 changes to ordering guide .......................................................... 13 12/12 rev. b to rev. c changes to figure 14 and figure 16 ............................................... 7 updated outline dimension s ....................................................... 12 changes to ordering guide .......................................................... 13 6/ 10 rev. a to rev. b added exposed pad notation to figure 4 and table 3 ................ 5 added exposed pad notation to outline dimensions ............. 12 changes to ordering guide .......................................................... 13 1/0 4 rev. 0 t o rev. a format u pdated .................................................................. universal renumbered f igure s .......................................................... universal removed figure 22 ............................................................................ 6 change to printed circuit board layout considerations s ection .............................................................................................. 11 added lfcsp layout considerations s ection ........................... 11 added package drawing ................................................... universal changes to ordering guide .......................................................... 16
data sheet adp3335 rev. d | page 3 of 16 specifications all limits at temperature ext remes are guaranteed via correlation using standard statistical quality control (sqc) methods. ambient temperature of 85 c corresponds to a junction temperature of 125 c under pulsed full - load test conditions. application stable with no load. v in = 6.0 v, c in = c out = 1.0 f, t a = C 40c to +85c, unless otherwise noted. table 1. parameter symbol conditions min typ max unit output voltage accuracy 1 v out v in = v out(nom) + 0.4 v to 12 v C0.9 +0.9 % i l = 0.1 ma to 500 ma t a = 25c v in = v out(nom) + 0.4 v to 12 v C1.8 +1.8 % i l = 0.1 ma to 500 ma t a = 85c v in = v out(nom) + 0.4 v to 12 v C2.3 +2.3 % i l = 0.1 ma to 500 ma t j = 150c line regulation 1 v in = v out(nom) + 0.4 v to 12 v 0.04 mv/v i l = 0.1 ma t a = 25c load regulation i l = 0.1 ma to 500 ma 0.04 mv/ma t a = 25c dropout voltage v drop v out = 98% of v out(nom) i l = 500 m a 200 370 mv i l = 300 ma 140 230 mv i l = 50 ma 30 110 mv i l = 0.1 ma 10 40 mv peak load current i ldpk v in = v out(nom) + 1 v 800 ma output noise v noise f = 10 hz to 100 khz, c l = 10 f 47 v rms i l = 500 ma, c nr = 10 nf f = 10 hz to 100 khz, c l = 10 f 95 v rms i l = 500 ma, c nr = 0 nf ground current in regulation i gnd i l = 500 ma 4.5 10 ma i l = 300 ma 2.6 6 ma i l = 50 ma 0.5 2.5 ma i l = 0.1 ma 80 110 a in dropout i gnd v in = v out(nom) C 100 mv 120 400 a i l = 0.1 ma in shutdown i gndsd sd = 0 v, v in = 12 v 0.01 1 a shutdown threshold voltage v thsd on 2.0 v o ff 0.4 v sd input current i sd 0 sd 5 v 1.2 3 a output current in shutdown i osd v in = 12 v, v out = 0 v 0.01 5 a 1 v in = 2.6 v to 12 v for models with v out(nom) 2.2 v.
adp3335 data sheet rev. d | page 4 of 16 absolute maximum rat ings table 2. parameter rating input supply voltage C 0.3 v to +16 v shutdown input voltage C 0.3 v to +16 v power dissipation internally limited operating ambient temperature range C 40c to +85c operating junction temperature range C 40c to +150c ja , 2- layer msop -8 220c/w ja , 4- layer msop -8 158c/w ja , 2 - layer lfcsp - 8 62c/w ja , 4- layer lfcsp -8 48c/w storage temperature range C 65c to +150c lead temperature range (soldering 10 sec) 300c vapor phase (60 sec) 215c infrared (15 sec) 220 c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of th is specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
data sheet adp3335 rev. d | page 5 of 16 pin configuration an d function descripti ons adp3335 top view (not to scale) out 1 out 2 out 3 gnd 4 in in sd nr 8 7 6 5 00147-0-022 figure 3 . 8 - lead msop s d 1 2 3 4 7 8 6 5 t o p v i e w ( n o t t o s c a l e ) o u t o u t g n d i n i n n r a d p 3 3 3 5 o u t 0 0 1 4 7 - 0 - 0 2 5 n o t e s 1 . t h e e x p o s e d p a d o n t h e b o t t o m o f t h e p a c k a g e e n h a n c e s t h e t h e r m a l p e r f o r m a n c e a n d i s e l e c t r i c a l l y c o n n e c t e d t o d i e s u b s t r a t e . t h e r m a l v i a s m u s t b e i s o l a t e d o r c o n n e c t e d t o i n . d o n o t c o n n e c t t h e t h e r m a l p a d t o g r o u n d . figu re 4 . 8 - lead lfcsp table 3 . pin function descriptions pin no. mnemonic function 1, 2, 3 out output of the regulator. bypass to ground with a 1.0 f or larger capacitor. all pins must be connected toge ther for proper operation. 4 gnd ground pin. 5 nr noise reduction pin. used for further reduction of output noise (see the noise reduction section for further details). 6 sd active low shutdown pin. connect to ground to disabl e the regulator output. when shutdown is not used, this pin should be connected to the input pin. 7, 8 in regulator input. all pins must be connected together for proper operation. ep exposed pad the exposed pad on the bottom of the lfcsp package enha nces thermal performance and is electrically connected to the die substrate, which is electrically common with the input pins, in (pin 7 and pin 8), inside the package.
adp3335 data sheet rev. d | page 6 of 16 typical performance characteristics t a = 25c, unless otherwise noted . 00147-0-003 v out = 2.2v i l = 0 150ma 300ma 500ma 2.202 2.201 2.200 2.199 2.198 2.197 2.196 2.195 2.194 input voltage (v) output voltage (v) 2 4 6 8 10 12 figure 5 . line regulation output voltage vs. supply voltage 00147-0-004 v out = 2.2v v in = 6v 2.201 2.200 2.199 2.198 2.197 2.196 2.195 2.194 2.193 load current (ma) output voltage (v) 0 100 200 300 400 500 figure 6 . output voltage vs. load current 00147-0-005 140 120 100 80 60 40 20 0 input voltage (v) ground current ( a) 2 4 6 8 10 12 v out = 2.2v i l = 0 i l = 100a 0 figure 7 . ground current vs. supply voltage 00147-0-006 5.0 4.0 3.0 2.0 1.0 0 load current (ma) ground current ( a) 0 100 200 300 400 500 figure 8 . ground current vs. load current 00147-0-007 ? 0.4 junction temperature ( c) output change (%) ? 40 45 65 85 105 125 ? 0.3 ? 0.2 ? 0.1 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 0 1.0 ? 15 5 25 500ma 500ma 300ma 0 figure 9 . output voltage variation vs. junction temperature 00147-0-008 junction temperature ( c) ground current (ma) ? 40 45 65 85 105 125 1 2 3 4 5 6 7 0 8 ? 15 5 25 300ma 50ma i l = 500ma 0 100ma figure 10 . ground current vs. junction temperature
data sheet adp3335 rev. d | page 7 of 16 00147-0-009 output ( ma) dropout voltage (mv) 0 400 500 0 50 100 150 200 250 100 200 300 figure 11 . dropout voltage vs. output current 00147-0-010 time ( sec) input/output voltage (v) 4 0 0.5 1.0 1.5 2.0 2.5 1 2 3 3.0 v out = 2.2v sd = v in r l = 4.4 ? figure 12 . power - up/power - down 00147-0-011 time (s) v in (v) 400 200 0 2 4 0 1 800 600 2 v out = 2.2v sd = v in r l = 4.4? 3 c out = 10f c out = 1f v out (v) figure 13 . power - up response 00147-0-012 time ( s) v out (v) 80 40 3.000 3.500 2.170 2.180 2.190 180 140 2.200 v out = 2.2v r l = 4.4 ? c l = 1 f 2.210 v in (v) figure 14 . line transient response 00147-0-013 time ( s) v out (v) 80 40 3.000 3.500 2.179 2.189 2.190 180 140 2.200 v out = 2.2v r l = 4.4 ? c l = 10 f 2.210 v in (v) figure 15 . l ine transient response 00147-0-014 time ( s) i load (ma) 400 200 0 200 400 2.1 800 600 2.2 v in = 4v r l = 2.2 ? c l = 1 f 2.3 v out (v) figure 16 . load transient response
adp3335 data sheet rev. d | page 8 of 16 00147-0-015 time ( s) i load (ma) 400 200 0 200 400 2.1 800 600 2.2 v in = 4v r l = 4.4 ? c l = 10 f 2.3 v out (v) figure 17 . load transient response 00147-0-016 time ( s) 400 200 1 2 3 0 800 600 0 2.2 v in = 4v full short 800m ? short i load (a) v out (v) figure 18 . short - circuit current 00147-0-017 time ( s) v sd (v) 400 200 0 1 2 1 800 600 2 3 v out (v) v in = 4v v out = 2.2v r l = 4.4 ? 1 f 10 f 10 f 1 f figure 19 . turn on/turn off response 00147-0-018 ? 40 ? 50 ? 60 ? 70 ? 80 ? 90 frequency (hz) ripple rejection (db) 10 1k 10k 100k 1m 10m ? 20 ? 30 100 v out = 2.2v c l = 1 f i l = 50 a c l = 1 f i l = 500ma c l = 10 f i l = 500ma c l = 10 f i l = 50 a figure 20 . power supply ripple rejection 00147-0-019 i l = 500ma with noise reduction i l = 500ma without noise reduction i l = 0ma without noise reduction i l = 0ma with noise reduction c nr = 10nf 160 140 120 100 80 60 40 20 0 c l (f) rms noise (v) 0 10 20 30 40 50 figure 21 . rms noise versus c l (10 hz to 100 khz) 00147-0-020 100 10 1 0.1 0.01 0.001 frequency (hz) voltage noise spectral density ( v/ hz) 10 1k 10k 100k 1m 100 v out = 2.2v i l = 1ma c l = 10 f c nr = 10nf c l = 1 f c nr = 0nf c l = 10 f c nr = 0nf c l = 1 f c nr = 10nf figure 22 . output noise density
data sheet adp3335 rev. d | page 9 of 16 theory of ope ration the adp3335 uses a single control loop for regulation and reference functions. the output voltage is sensed by a resistive voltage divider, r1 and r2, which is varied to provide the ava ilable output voltage option. feedback is taken from this network by way of a series diode, d1, and a second resistor divider, r3 and r4, to the input of an amplifier. input 00147-0-023 output compensation capacitor r2 r1 gnd adp3335 ptat current r4 ptat v os g m q1 attenuation (v bandgap /v out ) r3 d1 (a) c load r load noninverting wideband driver figure 23 . functional block diagram a very high gain error am plifier is used to control this loop. the amplifier is constructed in such a way that equilibrium produces a large, temperature proportional input offset voltage that is repeatable and very well controlled. the temperature proportional offset voltage combi nes with the complementary diode voltage to form a virtual band gap voltage implicit in the network, although it never appears explicitly in the circuit. this patented design makes it possible to control the loop with only one amplifier. this technique als o improves the noise characteristics of the amplifier by providing more flexibility in the trade - off of noise sources that leads to a low noise design. the r1 and r2 divider is chosen in the same ratio as the band gap voltage to the output voltage. althoug h the r1 and r2 resistor divider is loaded by the d1 diode and a second divider r3 and r4, the values can be chosen to produce a temperature stable output. this unique arrangement specifically corrects for the loading of the divider, thus avoiding the erro r resulting from base current loading in conventional circuits. the patented amplifier controls a new and unique noninverting driver that drives the pass transistor, q1. this special noninverting driver enables the frequency compensation to include the loa d capacitor in a pole - splitting arrangement to achieve reduced sensitivity to the value, type, and esr of the load capacitance. most ldos place very strict requirements on the range of esr values for the output capacitor, because they are difficult to stab ilize due to the uncertainty of load capacitance and resistance . the esr value required to keep conventional ldos stable, moreover, changes depending on load and temperature. these esr limitations make designing with ldos more difficult because of their un clear specifications and extreme variations over temperature. with the adp3335 , esr limitations are no longer a source of design constraints. the adp3335 can be used with virtually any good quality capacitor and with no constraint on the minimum esr. this innovative design allows the circuit to be stable with just a small 1 f capacitor on the output. additional advantages of the pol e - splitting scheme include superior line noise reject - tion and very high regulator gain, which lead to excellent line and load regulation. impressive 1.8% accuracy is guaranteed over line, load, and temperature. additional features of the circuit include current limit, thermal shutdown, and noise reduction.
adp3335 data sheet rev. d | page 10 of 16 applications information output capacitor sel ection as with any micropower device, output transient response is a function of the output capacitance. the adp3335 is stable over a wide range of capacitor values, types, and esr (anycap). a capacitor as low as 1 f is all that is needed for stability; larger capacitors can be used if high output current surges are anticipated . the adp3335 is stable with ex tremely low esr capacitors (esr 0), such as multilayer ceramic capacitors (mlcc) or organic semiconductor electrolytic capacitors (oscon). note that the effective capacitance of some capacitor types may fall below the minimum at extreme temperatures. ensure that the capacitor prov ides more than 1 f over the entire temperature range. input bypass capacit or an input bypass capacitor is not strictly required, but is advisable in any application involving long input wires or high source impedance. connecting a 1 f capacitor from in to ground reduces the circuits sensitivity to pc board layout. if a larger value output capacitor is used, then a larger value input capacitor is also recommended. noise reduction a noise reduction capacitor (c nr ) can be used, as shown in figure 24 , to further reduce the noise by 6 db to 10 db ( figure 22 ). low leakage capacitors in the 100 pf to 1 nf range provide the best performance. since the noise reduction pin, nr, is in ternally connected to a high impedance node, any connection to this node should be made carefully to avoid noise pickup from external sources. the pad connected to this pin should be as small as possible, and long pc board traces are not recommended. when adding a noise reduction capacitor, maintain a minimum load current of 1 ma when not in shutdown. it is important to note that as c nr increases, the turn - on time will be delayed. with nr values greater than 1 nf, this delay may be on the order of several m illiseconds. nr in in out out out gnd sd adp3335 on off v in c in 1f + + v out 00147-0-021 1 3 4 7 2 5 6 8 c out 1f c nr figure 24 . typical application circuit thermal overload pro tection the adp3335 is protected against damage from excessive power dissipation by its th ermal overload protection circuit, which limits the die temperature to a maximum of 165 c. under extreme conditions (i.e., high ambient temperature and power dissipation) where die temperature starts to rise above 165 c, the output current is reduced until the die temperature has dropped to a safe level. the output current is restored when the die temperature is reduced. current and thermal limit protections are intended to protect the device against accidental overload conditions. for normal operation, dev ice power dissipation should be externally limited so that junction temperatures will not exceed 150 c. calculating junction temperature device power dissipation is calculated as follows: p d = (v in ? v out ) i load + (v in ) i gnd where i load and i gnd are load cu rrent and ground current, and v in and v out are input and output voltages, respectively. assuming i load = 400 ma, i gnd = 4 ma, v in = 5.0 v, and v out = 3.3 v, device power dissipation is p d = (5 v C 3.3 v)400 ma + 5.0 v(4 ma) = 700 mw the junction temperatur e can be calculated from the power dissipation, ambient temperature, and package thermal resistance . the thermal resistance is a function not only of the package, but also of the circuit board layout. standard test conditions are used to determine the valu es published in this data sheet, but actual performance will vary. for an lfcsp - 8 package mounted on a standard 4 - layer board, ja is 48 c/w. in the above example, where the power dissipation is 700 mw, the temperature rise above ambient will be approximat ely equal to ? t ja = 0.700 w 48c/w = 33.6c to limit the maximum junction temperature to 150 c, the maximum allowable ambient temperature will be t amax = 150c ? 33.6c = 116.4c in this case, the resulting ambient temperature limitation is above the max imum allowable ambient temperature of 85 c.
data sheet adp3335 rev. d | page 11 of 16 printed circuit boar d layout considerations all surface - mount packages rely on the traces of the pc board to conduct heat away from the package. use the following general guidelines when designing printed circuit boards to improve both electrical and thermal performance. 1. keep the output capacitor as close as possible to the output and ground pins. 2. keep the input capacitor as close as possible to the input and ground pins. 3. pc board traces with larger cross s ectional areas will remove more heat from the adp3335 . for optimum heat transfer, specify thick copper and use wide traces. 4. it is not recommended to use solder mask or silkscreen on the pcb tra ces adjacent to the adp3335 s pins, since doing so will increase the junction - to - ambient thermal resistance of the package. 5. use additional copper layers or planes to reduce the thermal resistan ce. when connecting to other layers, use multiple vias, if possible. lfcsp layout conside rations the lfcsp package has an exposed die paddle on the bottom, which efficiently conducts heat to the pcb. in order to achieve the optimum performance from the lfc sp package, special consideration must be given to the layout of the pcb. use the following layout guidelines for the lfcsp package. 0. 50 2 vias, 0.250 ? 35 m pla ting 3.36 0.90 1.80 2.36 1.90 1.40 0. 30 0 . 7 3 00147-0-024 figure 25 . 3 mm 3 mm lfcsp pad pattern (dimensions shown in millimeters) 1. the pad pattern is gi ven in figure 25 . the pad dimension should be followed closely for reliable solder joints, while maintaining reasonable clearances to prevent solder bridging. 2. the thermal pad of the lfcsp package provides a low thermal impedance pa th (approximately 20c/w) to the pcb. therefore, the pcb must be properly designed to effectively conduct heat away from the package. this is achieved by adding thermal vias to the pcb, which provide a thermal path to the inner or bottom layers. see figure 25 for th e recommended via pattern. note that the via diam eter is small to prevent the solder from flowing through the via and leaving voids in the thermal pad solder joint. also, note that the thermal pad is attached to the die s ubstrate , so the thermal planes to which the thermal vias connect must be electrically isolated or tied to v in . do not connect the thermal pad to ground. 3. the solder mask opening should be about 120 (4.7 mils) larger than the pad size, resulting in a mini mum 60 m (2.4 mils) clearance between the pad and the solder mask. 4. the paste mask opening is typically designed to match the pad size used on the peripheral pads of the lfcsp package. this should provide a reliable solder joint as long as the stencil thic kness is about 0.125 mm. the paste mask for the thermal pad needs to be designed for the maximum coverage to effectively remove the heat from the package. however, due to the presence of thermal vias and the size of the thermal pad, eliminating voids may n ot be possible. 5. the recommended paste mask stencil thickness is 0.125 mm . a laser cut stainless steel stencil with trapezoidal walls should be used. a no clean type 3 solder paste should be used for mounting the lfcsp package. also, a nitrogen purge duri ng the reflow process is recommended. 6. the package manufacturer recommends that the reflow temperature should not exceed 220c and the time above liquidus is less than 75 seconds. the preheat ramp should be 3c/second or lower. the actual temperature profil e depends on the board density and must be determined by the assembly house as to what works best. shutdown mode applying a ttl high signal to the shutdown ( sd ) pin or tying it to the input pin, turns the output on. pulling sd down to 0.4 v or below, or tying it to ground, turns the output off. in shutdown mode, quiescent current is reduced to a typical value of 10 na.
adp3335 data sheet rev. d | page 12 of 16 outline dimensions t o p v i e w 8 1 5 4 0 . 3 0 0 . 2 5 0 . 2 0 b o t t o m v i e w p i n 1 i n d e x a r e a s e a t i n g p l a n e 0 . 8 0 0 . 7 5 0 . 7 0 1 . 5 5 1 . 4 5 1 . 3 5 1 . 8 4 1 . 7 4 1 . 6 4 0 . 2 0 3 r e f 0 . 0 5 m a x 0 . 0 2 n o m 0 . 5 0 b s c e x p o s e d p a d 3.10 3.00 sq 2.90 for prope r conne cti on of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. copla narit y 0.08 0.50 0.40 0.30 compliant t o jedec standard s mo-229-we ed 12-07-2010-a pin 1 indica t or (r 0.15) figure 26 . 8 - lead lead frame chip scale package [lfc sp _ w d] 3 mm 3 mm body, very very thin, dual lead (cp - 8 - 13) dimensions shown in millimeters complian t to jedec standards mo-187-aa 100709 -b 6 0 0.80 0.55 0.40 4 8 1 5 0.65 bsc 0.40 0.25 1.10 max 3.20 3.00 2.80 coplanarity 0.10 0.23 0.09 3.20 3.00 2.80 5.15 4.90 4.65 pin 1 identifi er 15 max 0.95 0.85 0.75 0.15 0.05 figure 27 . 8 - lead mini small outline package [msop] (rm - 8) dimensions shown in millimeters
data sheet adp3335 rev. d | page 13 of 16 ordering guide model 1 output voltage (v) 2 temperature range package description package option branding 3 adp3335acpz - 1.8-r7 1.8 C 40c to +85c 8- lead lfcsp_ w d cp -8-13 l1g adp3335acpz - 2.5 - r7 2.5 C 40c to +85c 8 - lead lfcsp_ w d cp - 8 - 13 l1h adp3335acpz - 2.85r7 2.85 C 40c to +85c 8- lead lfcsp_ w d cp -8-13 l1j adp3335acpz - 3.3-r7 3.3 C 40c to +85c 8- lead lfcsp_ w d cp -8-13 l1k adp3335acpz - 3.3-rl 3.3 C 40c to +85c 8- lead lfcsp_ w d cp -8-13 l1k adp3335acpz - 5-r7 5 C 40c to +85c 8- lead lfcsp_ w d cp -8-13 l1l adp3335armz - 1.8-r7 1.8 C 40c to +85c 8-le ad msop rm -8 lfa adp3335armz - 1.8-rl 1.8 C 40c to +85c 8- lead msop rm -8 lfa adp3335armz - 2.5-rl 2.5 C 40c to +85c 8- lead msop rm -8 lfc adp3335armz - 2.5rl7 2.5 C 40c to +85c 8- lead msop rm -8 lfc adp3335armz - 2.85r7 2.85 C 40c to +85c 8- lead msop rm -8 lfd adp3335armz - 2.85rl 2.85 C 40c to +85c 8- lead msop rm -8 lfd adp3335armz - 3.3 - rl 3.3 C 40c to +85c 8 - lead msop rm - 8 lfe adp3335armz - 3.3rl7 3.3 C 40c to +85c 8- lead msop rm -8 lfe adp3335armz - 5-r7 5 C 40c to +85c 8- lead msop rm -8 lff adp3335armz - 5- reel 5 C 40c to +85c 8- lead msop rm -8 lff 1 z = rohs compliant part . 2 for additional voltage options, contact a local sales or distribution representative . 3 z = rohs compliant parts have a "#" marked on the device preceding the date code.
adp3335 data sheet rev. d | page 14 of 16 notes
data sheet adp3335 rev. d | page 15 of 16 notes
adp3335 data sheet rev. d | page 16 of 16 notes ? 2000 C 2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d00147 - 0- 10/13(d)

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